The present invention in some aspects relates to gain-boosted operational amplifiers (opamps). In other aspects, the invention relates to opamps for pipelined analog-to-digital converters (ADCs).
Operational amplifiers are employed in many different types of devices. For example, wireless communications systems have base station receiver chains that employ analog-to-digital converters (ADCs), and each ADC may employ opamps. The pipelined ADC architecture is employed to build high speed and high resolution ADCs, each having an analog core which employs high gain, high frequency opamps.
Pipelined ADCs have become a de facto standard in base station receiver chains for wireless communication systems. The pipelined ADC has a fast architecture, and is believed to provide a fair compromise among resolution, power consumption, and conversion speed.
In certain contexts, such as in base station receiver chains implemented in a miniaturized integrated circuit (IC) (such as an SOC (system on a chip)), there is a desire to scale down the voltage supply of the pipelined ADC.
Pipelined ADCs and their components, particularly the opamps they employ, continue to evolve. Efforts are underway to reduce the voltage supply level required for the pipelined ADC to levels at 3.3V and below, to allow further miniaturization of the integrated circuit (IC) and to lead to inclusion of such devices in an SOC (system on a chip). Meanwhile, the gain levels for these pipelined ADCs are beyond 80 dB for ADC resolutions of 12 or more bits per word, while the intrinsic gain for a given transistor may be well below 30 dB. Add to these constraints the continued necessity that these circuits operate well at high speeds.
Various pipelined ADCs have been designed to attain higher gains and speeds. To this end, various improved opamp structures are being introduced, including one-stage telescopic amplifiers, opamps with a single stage preceded by low-gain preamplifiers, or two-stage opamp architectures. In each of these opamp structures, some form of cascoding is adopted on the main gain stage, to make up for a reduced output impedance of the transistors (i.e. reduced Early voltage). This approach also takes advantage of the better transconductance (gm) of short-channel transistors.
The following references describe examples of opamp structures generally taking this approach.    [1] A. Loloee, A. Zanchi, H. Jin, S. Shehata, and E. Bartolome, “A 12 b 80 MSps Pipelined ADC Core With 190 mW Consumption from 3V in 0.18 μm Digital CMOS”, in Proceedings of the IEEE European Solid-State Circuits Conference (ESSCIRC 2002), Florence (Italy), Sep. 24–26, 2002, pp. 467–470.    [2] B. M. Min, P. Kim, D. Boisvert, and A. Aude, “A 69 mW 10 b 80 MS/s Pipelined CMOS ADC ”, IEEE ISSCC Digest of Technical Papers, San Francisco, Calif., February 2003, pp. 324–325.    [3] A. R. Bugeja and S. U. Kwak, “Design of a 14 b 100 MS/s Switched-capacitor Pipelined ADC in RFSiGe BiCMOS”, in Proceedings of the ISCAS 2001, Sydney, Australia, May 2001, pp. 428–431.    [4] L. Singer, S. Ho, M. Timko, and D. Kelly, “A 12 bit 65 Msample/s CMOS ADC with 82 dB SFDR at 120 MHz”, in ISSCC Digest of Technical Papers, San Francisco, Calif., February 2000, pp. 38–39.    [5] A. Zanchi, F. Tsay, and I. Papantonopoulos, “Impact of Capacitor Dielectric Relaxation on a 14-bit, 70-MSps Pipeline ADC in 3-V BiCMOS”, in press for IEEE Journal of Solid-State Circuits, December 2003.    [6] D. Kelly, W. Yang, I. Mehr, M. Sayuk, and L. Singer, “A 3V 340 mW 14 b 75 MSps CMOS ADC with 85 dB SFDR at Nyquist”, in ISSCC Digest of Technical Papers, San Francisco, Calif., February 2001, pp. 134–135.
Existing opamp structures, such as those identified above, may not sufficiently boost their gain, with a requisite level of performance. Accordingly, other techniques may be employed to facilitate gain-boosting, including using an auxiliary amplifier to reinforce the output impedance of the principal transconductance amplifier. This is discussed, for example, by Bult et al., “A Fast-settling CMOS Opamp for SC Circuits With 90-dB DC Gain”, IEEE Journal of Solid-State Circuits, Vol. 25, December 1990, pp. 1379–1384.
Popular circuits which provide a gain-boosting function include a single-ended common-source stage as disclosed by Bugeja et al. (see citation above), or a form of differential folded-cascode servo-amp, as disclosed by Loloee et al. (citation above), or Min et al. (citation above).
These solutions generally share a common problem of pole-zero doublet compression. Apfel et al., “A Fast-settling Monolithic Operational Amplifier Using Doublet Compression Techniques”, IEEE Journal of Solid-State Circuits, Vol. 9, No. 6, December 1974, pp. 332–340.
Doublet compression can be relieved by placing a capacitor (otherwise referred to as a compensation capacitor) within the loop of the booster to limit its bandwidth of response. This prevents the doublet from approaching the second pole of the main opamp, and moves the pole and zero closer to each other in absolute terms. The result is that the opamp AC response has a smoother phase profile.
Opamp structures will typically also “ballast” the internal voltage reference nodes generated by the bias network of the opamp (often a series of diodes) with a localized capacitor. This is done to filter out voltage spikes propagating from the power supply, and to limit the high frequency noise as much as possible.
FIG. 1 is a schematic of a background amplification circuit, improved upon by employing circuits later illustrated in FIGS. 2 and 3. The illustrated circuit comprises a one stage BiCMOS opamp. The illustrated opamp 10 comprises bias circuitry 12 and an output stage 14. The illustrated output stage 14 comprises transductance elements 16, corresponding cascode elements 18, current source elements (active load) 20, corresponding cascode elements of the load 26, and gain boosters 24.
Current source elements 20 are connected to corresponding current source cascode elements 26, which are in turn connected to transconductance elements 16 via respective corresponding cascode elements 18. Tail elements 22 are provided between transconductance elements 16 and a reference voltage node AVSS, which is zero volts in the illustrated embodiment. Current source elements 20 are coupled to a DC power supply AVDD, which in the illustrated embodiment is 3.3V.
In the illustrated amplification circuit 10, bias circuitry 12 comprises a bias node 13 connected to the base of each of corresponding cascode elements 18, which correspond to transconductance elements 16. Cascode elements 18 and their corresponding transductance elements 16 form part of output stage 14. Bias circuitry 12 further comprises a current source 28 and a set of interconnected diode elements. In the simplified circuit illustrated, those diode elements are n type and p type transistor elements, specifically comprising PMOS field effect transistors (FETs) T1 and T2, an npn bipolar junction transistor (BJT) T11, and NMOS field effect transistor (FETs) T14, T17, and T18.
Transconductance elements 16 comprise npn BJTs T15 and T16. Tail elements 22 comprise NMOS FETs T19 and T20. Corresponding cascode elements 18 comprise npn BJTs T12 and T13. Current source elements 20 comprise PMOS FETs T3 and T4. Corresponding source cascode elements 26 comprise PMOS FETs T5 and T8.
The illustrated amplification circuit 10 serves as a differential amplifier with differential inputs, the amplification of which is represented across the differential outputs. In the illustrated embodiment, the differential inputs comprise INp (Vin-p) and INn (Vin-n), which comprise the respective bases of transconductance elements 16. The illustrated circuit further comprises outputs OUTn (Vout-n) and OUTp (Vout-p), located at which points between the drains of corresponding current source cascode elements 26 and the collectors of cascode elements 18.
The illustrated circuit 10 further comprises gain boosters 24. Each booster 24 is connected between a sense node 29 at its input, to read the intermediate voltage between load 20 and respective cascode element 26; and a driven node 25 at its output, to control the node's voltage level forming a feedback loop around the cascode element 26, which increases its output impedance. The boosters 24 are supplied by the same voltages AVDD and AVSS as the whole opamp, whereby AVDD is 3.3V and AVSS is 0V in the illustrated embodiment. Boosters 24 are respectively connected to outputs OUTn and OUTp via the corresponding current source cascode elements 26. Gain boosters 24 serve to increase the impedance across the output of the circuit, thereby increasing the amplification of the voltage signal between the input terminals and the output terminals. Specifically, the gain is equal to [(Vout-p)−(Vout-n)]/[(Vin-p−Vin-n)]. The illustrated circuit 10 comprises a set of circuit elements that form a P-block, meaning that the elements contained within that portion of output stage 14 are generally P type elements (PMOS FETs, pnp BJTs). Another set of elements form an N-block meaning that those elements are generally N type elements (NMOS FETs, npn BJTs).
In the illustrated circuit, the active loads implemented in the P-block comprise respective gain booster portions 24. In the circuit of FIG. 1, gain booster portions 24 comprise two single-ended servo-opamps.
FIG. 3 presents AC response plots for the operational amplifier shown in FIG. 1. Specifically, the smoothness of the phase plot of the amplifier (and consequently its phase margin) can be improved by increasing the capacitances value of the compensation capacitor 30 within the one stage operational amplifier shown in FIG. 1. This is confirmed by the waveforms shown in FIG. 3, which illustrates the gain AC response and the phase AC response of the noted circuit, for different compensation capacitor values ranging from as high as 7 picofarads to as low as 1 attofarads (lowest curve in the phase plot). The higher compensation capacitor value of 7 picofarads results in the better waveform AC responses, particularly a better phase response. It is beneficial to increase the amount of capacitance of the compensation capacitor. Specifically, by increasing the amount of capacitance, the long-term voltage ringing at the output of the differential amplifier can be zeroed out. Analogously, increasing the amount of capacitance of the capacitor decoupling the bias node 13 toward a steady voltage (AVSS in the illustrated embodiment) enhances the common-mode stability of the amplifier 10.